How chips are made, in diagrams.

A plain-language guide to wafers, chips, fabs, OSAT and ATMP. Six labelled diagrams take you from a slice of silicon to a packaged, tested part.

01 The journey

Fifteen stations from silicon to shipment.

The front-end builds the chip on the wafer, layer by layer. The back-end cuts it out, connects it, protects it and tests it.

Front-end In the wafer fab

01WaferA polished slice of a silicon crystal.
02Design and masksThe chip’s layers, drawn as photomasks.
03DepositA thin film is grown or laid down.
04PatternLithography prints the layer’s pattern.
05EtchUnprotected material is removed.
06ImplantIons change the silicon’s properties.
07PolishThe surface is flattened for the next layer.
08InspectEvery layer is measured and checked.
09Wafer sortEvery die is tested before it leaves.

Steps 03 to 08 repeat for every layer of the chip, dozens of times, before wafer sort.

Back-end In the OSAT or ATMP line

01Grind and diceThe wafer is thinned and cut into dies.
02Die attachGood dies are fixed to a frame or substrate.
03InterconnectWire bonds or bumps make the connections.
04MoldThe assembly is sealed in compound.
05Final testEach packaged part is tested, some after burn-in.
06Mark and shipMarked, inspected, packed, shipped.

Fig. 01The route of a chip. Front-end steps happen in the wafer fab; back-end steps in an OSAT or ATMP facility.

02 The wafer

One wafer, many dies.

Every copy of the chip is printed side by side on a polished silicon disc. Most of what a fab measures, it measures per die.

1Die. One copy of the chip. A wafer carries many.
2Scribe line. The lane between dies, cut away at dicing.
3Reticle field. What one lithography exposure prints, here six dies.
4Edge exclusion. A ring near the edge where dies are not usable.
5Partial die. Cut off by the edge, so never shipped.
6Notch. Tells every tool which way the wafer is turned.
7Test site. Structures used to check the process, not sold.

Fig. 02Anatomy of a wafer. The highlight stepping across the dies is a prober testing them one by one at wafer sort.

03 Inside a chip

Switches at the bottom, wiring on top.

The transistors sit in the silicon surface. Above them, layer upon layer of copper wiring connects them. The front-end-of-line builds the first; the back-end-of-line builds the second.

1Silicon substrate. The wafer itself, with doped wells.
2Transistors. The switches, built into the wafer surface.
3Contacts. Tungsten plugs from transistors to the first metal.
4Local wiring. The finest metal lines, linking nearby transistors.
5Intermediate wiring. Routes signals across blocks of the chip.
6Global wiring. Thick top layers carry power and long signals.
7Vias. Vertical copper plugs between metal layers.
8Passivation. A hard layer that seals the finished die.
9Bond pad. Where the chip meets its package, here by wire.

Fig. 03A chip in cross-section, not to scale. The white pulse is a signal travelling from a transistor up to the bond pad.

04 Inside a fab

Three floors make one cleanroom work.

Air handling above, the cleanroom in the middle, the sub-fab below, and a utilities building beside it. The tools are only the visible part.

1Fan-filter ceiling. Filtered air flows down through the room without stopping.
2Overhead transport. Robotic vehicles carry wafer pods (FOUPs) between tools.
3Process tools. Deposition, lithography, etch, implant, polish and metrology.
4Gowned crews. Operators and technicians on every shift.
5Raised floor. Perforated, so air returns and services pass through.
6Vacuum pumps. In the sub-fab, below the tools they serve.
7Abatement. Treats tool exhaust before it leaves the building.
8Gas and chemical distribution. Cabinets and lines that feed every tool.
9Utilities. Ultrapure water, bulk gases, chillers and power.

Fig. 04A wafer fab in cross-section, simplified. Filtered air flows down, wafer pods travel overhead, gases and chemicals rise from below.

05 Assembly and test

From wafer to package.

This is the work of OSAT and ATMP lines. Two common ways to connect the die: fine bond wires, or bumps under a flipped die.

01Grind and diceThe wafer is thinned and cut into dies.
02Die attachGood dies are fixed to a frame or substrate.
03InterconnectWire bonds or bumps make the connections.
04MoldThe assembly is sealed in compound.
05Final testEach packaged part is tested, some after burn-in.
06Mark and shipMarked, inspected, packed, shipped.

Fig. 05The back-end line, station by station.

1Die. Face up, connected from its top edge.
2Die pad and attach. Metal pad and adhesive that hold the die.
3Bond wires. Fine gold or copper loops to the leads.
4Leads. Part of the leadframe; soldered to the board.
5Mold compound. Seals and protects everything inside.
6Flipped die. Face down, connected across its whole area.
7Bumps and underfill. Solder or copper bumps, with underfill around them.
8Substrate. A small circuit board that routes the signals.
9Solder balls. The grid that connects the package to the board.

Fig. 06Two packages in cross-section, not to scale: a wire-bonded leadframe package and a flip-chip ball grid array.

06 Fab, OSAT, ATMP

Three kinds of line, side by side.

OSAT and ATMP do the same work under different business models. A wafer fab is a different kind of factory altogether.

	Wafer fabFront-end	OSATBack-end, as a service	ATMPBack-end, captive
In	Bare wafers, gases, chemicals	Finished wafers from many customers	Finished wafers from the owner’s fabs
Out	Wafers carrying tested dies	Packaged, tested chips	Packaged, tested chips
Core steps	Deposit, pattern, etch, implant, polish, repeat	Dice, attach, bond, mold, test	Dice, attach, bond, mold, test
Cleanliness	Strictest: ISO class cleanrooms	Clean zones, less strict than a fab	Clean zones, less strict than a fab
People mix	Engineer- and technician-heavy	Operator-heavy at volume	Operator-heavy at volume
First hurdle	Process qualification and yield learning	Winning customer qualification	Meeting internal cost and quality targets

Every term, in the glossary OSAT, ATMP and advanced packaging

07 Questions

Chipmaking, answered plainly.

What is a wafer fab?

A wafer fab is a factory where chips are built on silicon wafers, layer by layer, inside a cleanroom. It is also called a front-end fab. Its output is wafers carrying many tested dies.

What is the difference between front-end and back-end semiconductor manufacturing?

Front-end manufacturing builds the chip on the wafer in a fab: deposition, lithography, etch, implant and polishing, repeated for every layer. Back-end manufacturing turns finished wafers into packaged, tested chips: dicing, die attach, wire bonding or flip-chip, molding, final test and marking.

What is a die?

A die is a single copy of the chip on a wafer. A wafer carries many dies, separated by scribe lines. After dicing, each good die is packaged into a chip.

What do OSAT and ATMP stand for?

OSAT stands for outsourced semiconductor assembly and test, a company that packages and tests chips for other companies. ATMP stands for assembly, testing, marking and packaging, a term usually used for a facility that does this work for its own company’s products.

What is the difference between wire bonding and flip-chip?

In wire bonding the die faces up and fine wires connect pads on its edge to the package leads. In flip-chip the die is turned face down and connected through bumps across its whole surface, which allows more connections and shorter paths.

What is a sub-fab?

The sub-fab is the floor below a fab’s cleanroom. It holds the vacuum pumps, exhaust abatement, gas cabinets and chemical distribution that serve the tools above.

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